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Low-power debugging made easy
The increasing complexity of power-aware SoC architectures makes it important to find efficient ways to debug their low-power elements. UPF provides a useful way to describe the power-management...
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Why emulation performance doesn’t matter (on its own)
A key reason for introducing hardware acceleration to a verification flow is performance. As SoC designs increase in size, the use of emulation and other hardware accelerators to analyze full-chip...
View ArticleTen key tips for effective memory verification
Increasingly complex bus, interface and memory access protocols are being used in SoCs to help meet demands to integrate more hardware functions and supporting software within tight power budgets....
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Hardware emulation gets smarter with save-and-restore for debug
Hardware emulation has come a long way recently but there remains room for improvement. Its use for debug is a good example. Debug rests on the ability to track the activity or waveforms of all the...
View ArticleDoc Formal: the crisis of confidence facing verification III
How to Optimize the Verification Meta Model II In the first two parts of this series, I described the verification crisis, explained how it came about, and began to describe the pillars and, within...
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Improve custom/AMS design and productivity with in-design DRC
As every IC designer knows, layout design verification gets exponentially harder with each process node. New manufacturing constraints, such as multi-patterning, impose new layout requirements, while...
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Doc Formal: Harness the power of invariant-based bug hunting
What’s the biggest design you can verify with formal? It’s a question I get asked a lot. The short answer I always give is it is not the size that matters but the micro-architecture of the design – and...
View ArticleDoc Formal: The budget case for formal verification
Axiomise launched its formal verification training program at the same time as the recent Verification Futures 2018 conference in the UK, where I set out a new vision for formal. Afterwards, I was...
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How to improve throughput for gate-level simulation
Gate-level simulation dates back to a simpler time when IC designs were, well, simple. At least by today’s standards. Yet, despite its age and relatively slow speeds, gate-level simulation remains...
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Doc Formal: Introducing the ADEPT FV flow
In an industry which responds to technology changes so swiftly, the changes in process take a long time to come through. We are designing cutting-edge technology in our chips that are driving the...
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Low-power debugging made easy
The increasing complexity of power-aware SoC architectures makes it important to find efficient ways to debug their low-power elements. UPF provides a useful way to describe the power-management...
View ArticleClik here to view.
Speed up design and verification with a smaller layout
Today’s large full-chip integrated circuit (IC) layouts can be very frustrating. Just viewing them requires powerful computers with substantial memory, and they are not always readily available. Even...
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A helping hand for design and verification
In the world of high technology, there is often an interesting interplay between the most popular consumer products and the most advanced devices and algorithms. For example, the near-ubiquitous...
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Correct design and verification coding errors as you type
There are few engineering tasks as daunting as the design and verification of a large, complex semiconductor device. A single designer may be responsible for millions of gates, with a combination of...
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A better way to debug P2P results
Thinking as a consumer rather than an engineer, what does product reliability mean to you? If you are like most people, you expect a product to work properly right out-of-the-box, and every time you...
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How IDEs enable the ‘shift left’ for VHDL
This series recently introduced the use of an integrated development environment (IDE) to develop designs and testbenches in the VHDL hardware description language. An IDE enables a more efficient...
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The path to full functional monitoring
The growing demands upon electronics system design are helping to chart a path towards platforms that will not only deliver optimal silicon but also allow far more detailed insights into how entire...
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Spiral in on silicon bugs in six formal steps
Winner of the Best Paper Award at DVCon US 2021, Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt shares the trade secrets of experienced formal verification...
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