FPGA prototyping
What is FPGA prototyping? FPGA prototyping is a well-established technique for verifying the functionality and performance of application-specific ICs (ASICs), application-specific standard products...
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How LTTng enables complex multicore system development
The Linux Trace Toolkit next generation (LTTng) tracer comes extremely close to addressing the issues that arise from increasing multicore system complexity during debug and performance optimization....
View ArticleDebugging the debug challenge
Around 70% of the effort involved in taping out a complex SoC is spent on verification. Of that effort, about half, or 35% of the total effort involved in a chip design, is spent on debug. Why is this?...
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Knock down the wall to SoC integration
Software engineers are too often treated as an afterthought in the SoC integration and verification process, in which hardware-software integration remains a rigidly serial process, despite software's...
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Debugging with virtual prototypes – Part One
This is the first of a series of articles on using virtual prototyping to debug embedded software. The articles that follow will focus on case studies that illustrate both techniques and advantages. To...
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Debugging with virtual prototypes – Part Two
To read Part One, which provides an introduction to core techniques for virtual prototypes, click here. To read Part Three, which illustrates the technique using examples addressing memory corruption,...
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Spot the difference between false and real clock violations
Clock domain crossings (CDCs) are a major source of complex SoC design errors that can and do easily slip past conventional verification tools and make their way into silicon. Thus it is essential to...
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Prototypers get faster route to first clock tick
Prototyping is increasingly important as designers strive to prove the functionality of their complex ASICs, confirm their compliance with complex industry standards, and will work as intended when...
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Accelerating ‘time to prototype’ with ProtoCompiler
Physical prototyping is becoming increasingly important to the consumer, wireless communications, industrial, and computation/storage markets, as well as to sectors such as wired communications,...
View ArticleThe budget case for emulation
It’s budget season. Annual reviews are well under way at many departments within semiconductor companies. It’s something most managers dread, a marathon of meetings spent justifying expediture and...
View ArticleBuilding better debug facilities for bigger FPGA-based prototypes
The introduction of Xilinx’s Virtex UltraScale VU440 FPGA may boost the capacity of FPGA-based prototyping, but it does little to help users debug a prototype. If anything, it increases the debug...
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Why emulation performance doesn’t matter (on its own)
A key reason for introducing hardware acceleration to a verification flow is performance. As SoC designs increase in size, the use of emulation and other hardware accelerators to analyze full-chip...
View ArticleTen key tips for effective memory verification
Increasingly complex bus, interface and memory access protocols are being used in SoCs to help meet demands to integrate more hardware functions and supporting software within tight power budgets....
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Hardware emulation gets smarter with save-and-restore for debug
Hardware emulation has come a long way recently but there remains room for improvement. Its use for debug is a good example. Debug rests on the ability to track the activity or waveforms of all the...
View ArticleDoc Formal: the crisis of confidence facing verification III
How to Optimize the Verification Meta Model II In the first two parts of this series, I described the verification crisis, explained how it came about, and began to describe the pillars and, within...
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Improve custom/AMS design and productivity with in-design DRC
As every IC designer knows, layout design verification gets exponentially harder with each process node. New manufacturing constraints, such as multi-patterning, impose new layout requirements, while...
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Doc Formal: Harness the power of invariant-based bug hunting
What’s the biggest design you can verify with formal? It’s a question I get asked a lot. The short answer I always give is it is not the size that matters but the micro-architecture of the design – and...
View ArticleThe budget case for formal verification
Axiomise launched its formal verification training program at the same time as the recent Verification Futures 2018 conference in the UK, where I set out a new vision for formal. Afterwards, I was...
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How to improve throughput for gate-level simulation
Gate-level simulation dates back to a simpler time when IC designs were, well, simple. At least by today’s standards. Yet, despite its age and relatively slow speeds, gate-level simulation remains...
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Doc Formal: Introducing the ADEPT FV flow
In an industry which responds to technology changes so swiftly, the changes in process take a long time to come through. We are designing cutting-edge technology in our chips that are driving the...
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